With advances in computing technology, computing devices are smaller and have much more processing power. Additionally, they include more and more storage and memory to meet the needs of the programming and computing performed on the devices. The shrinking size of the devices together with the increased storage capacity is achieved by providing devices with higher density, where there are more and more atomic storage units within a memory device, but each has smaller and smaller geometries.
Within the latest generation of increased density devices, intermittent failure has appeared in some devices. For example, some existing DDR3 (dual data-rate, version 3) based systems experience intermittent failures with heavy workloads. Researchers have traced the failures to repeated access to a single row of memory within the refresh window of the memory cell. For example, for a 32 nm process, if a row is accessed 550K times or more in the 64 ms refresh window, a physically adjacent wordline to the accessed row has a high probability of experiencing data corruption. The condition has been referred to as “row hammer” or “single row disturb” in the DRAM (dynamic random access memory) industry, where the condition is most frequently observed, and will be used to describe the condition generally herein. The row hammering can cause migration across the passgate. The leakage and parasitic currents caused by the repeated access to one row cause data corruption in a non-accessed physically adjacent row.
However, those skilled in the art also understand that memory devices vary among different generations of devices, among different manufacturers of comparable devices, and even among different batches within the same manufacturer. Thus, while heavy workloads have been observed to cause intermittent failures, there is no clear definition of “heavy workload” that applies to all devices. Thus, the row hammering condition is not clearly defined as a general parameter that applies to all devices.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.